1. Field of the Invention
The present invention relates to a memory controller, a memory system, and an access control method of a flash memory.
2. Description of the Related Art
Recently, non-volatile semiconductor memories are used in various devices ranging from large-scale computers to personal computers, home appliances, cellular phones or the like. A NAND flash memory in particular is a non-volatile, large capacity, and highly integrated semiconductor memory in which data can be rewritten electrically, and it is considered as an alternative to hard disk drives (HDDs).
JP-A 2007-87388 (KOKAI) discloses a data processing system that employs a NAND flash memory. In this data processing system, by control of a memory controller that controls a reading operation of a flash memory, data is transmitted from a flash memory having a buffer memory that temporarily stores page data to a dynamic random access memory (DRAM).
Typically, an error check and correction code (ECC) is added to data when writing the data in the NAND flash memory, and error check and correction is performed on the data by using the ECC in the data at the time of reading the data. The reliability of the NAND flash memory is increased by taking this approach.
At the time of writing write data into the NAND flash memory, because the write data is written after adding the ECC in the write data, when the write data is written in a situation where the data size of the write data is less than the page size of the NAND flash memory, there are cases that the data in the NAND flash memory cannot be read properly due to generation of an ECC error at the time of subsequent data reading. To take care of this issue, when the data size of the write data is less than the page size of the NAND flash memory, dummy data is added to the write data so that the total data size of the write data is equal to the page size of the NAND flash memory, and then the write data is written in the NAND flash memory. This procedure of writing the write data is performed by a central processing unit (CPU) that prepares the dummy data on a random access memory (RAM), i.e., a buffer, according to a management program (FW: firmware) and adds the dummy data to the write data.
However, when the dummy data is prepared on a RAM on the side of the FW, there is a rise in the usage of the RAM capacity for saving the dummy data and also a rise in the usage rate of a bus by an amount of dummy data when writing the write data into the NAND flash memory from the RAM, which makes it impossible for another master to access the RAM. There is another problem such that when the write data and the dummy data are prepared in a DRAM outside of a chip having a memory controller, the rate of accessing outside of an application specific integrated circuit (ASIC) chip is increased, which results in higher power consumption.